 Research
 Open access
 Published:
Post algebras and ternary adders
Journal of Electrical Systems and Information Technology volume 10, Article number: 20 (2023)
Abstract
Except for qubits for which the different possible values are unordered, the different values of mvalued circuits either with voltage levels, current levels or charge levels are totally ordered. Either at the Math level (Post algebras) or at the circuit level, it means that each multiple valued level must be decomposed into binary levels, processed with binary computation and finally converted into a multiple valued level. Using ternary adders as example, we show that the ternarytobinary decoding and binary encoding should be applied to the whole adder or to restricted parts of the adder. The second approach using multiplexers leads to the most efficient ternary adders. However, a comparison with binary adders shows that the ternarytobinary and binarytoternary conversions is the reason for which the binary adders are more efficient.
Introduction
Except for qubits, for which the different possible values are unordered, the different values of mvalued circuits are totally ordered. This is true whatever electrical support is used: voltage levels, current levels, number of charges. It means that the algebras corresponding to these m different values are some flavor of Post algebras. All variants of Post algebras decompose each multiple value into binary values. It means that the mvalued circuits use mvalued to binary decoders and binary to mvalued encoders. In this paper, the considered ternary full adders are compared to the corresponding binary ones. Two implementations of the ternary full adder are considered: a naive one and a MUXbased one. In both cases, ternarytobinary and binarytoternary conversions are used. The results can be easily extended to ternary multipliers or extended to quaternary adders or multipliers.
The paper is organized as follows:

Post algebra with 3 values is first presented.

Two opposite techniques to synthesize a ternary full adder are then presented

The methodology to compare MUXbased ternary adders and binary adders is presented

The performance of a ternary full adder using a “stateofthe art” technique is compared with the performances of binary full adders.

A 6bit carry propagate adder (CPA) is compared with a 4trit CPA.

The conclusion summarizes why ternary adders are less efficient than the corresponding binary ones processing the same amount of information.
Post algebras
Post algebra has been introduced in 1921 [1]. There exist several systems of Post algebra, which are isomorphic [2]. The monotonic system of Post algebra is used, as it is the most suitable for circuit implementation.
Monotonic system of Post algebra when \(m=3\)
The presentation is limited to \(m=3\) as the implementation of ternary circuits is studied.
Definition: Let \(m=3\). A monotonic algebraic system is a distributive lattice M with a null element 0 and a universal element 2 for which the following axioms are verified. To be consistent with the logical operators that will be presented later, the notation of the axioms is slightly changed while keeping their meaning.
Axiom 1: M has 3 elements \(e_0\), \(e_1\) et \(e_2\) such as

\(0=e_0<e_1<e_2=2\)

if \(x, e_i \in M\) and \(x.e_i = 0\) \((i \ne 0),\) then \(x=0\)

if \(x, e_i, e_j \in M\) and \(x + e_i = e_j\) \((i < j),\) then \(x=e_j\)
Axiom 2: There exist a set of unary operators \(X_n(x), X_p(x), \overline{X_n}(x), \overline{X_p}(x) \) such as

\(X_n(x) = 2\) if \(x < 1\) else 0 if \(x \ge 1\)

\(X_p(x) = 2\) if \(x < 2\) else 0 if \(x = 2)\)

\(\overline{X_n}(x) = 0\) if \(x < 1\) else 2 if \(x \ge 1)\)

\(\overline{X_p}(x) = 0\) if \(x < 2\) else 2 if \(x =2)\)
The unary operators translate a ternary input into a binary output, as shown in Table 1. The gates that implement the \(X_n\) and \(X_p\) unary operators are called negative inverter (NI) and positive inverter (PI). They are presented in Fig. 1. The binarytoternary conversion is implemented by the circuit shown in Fig. 2 corresponding to Table 3.
Synthesis of a ternary function
Let consider the example of the unary ternary function shown in Table 2.
\(y = y_2 + y_1\) where \(y_2\) is y(a) for which y=2 and \(y_1\) is y(a) for which y=1.

\(y_2 = a_0 = an \)

\(y_1 = a_1 = \overline{an}.ap\)
\( y = an + \overline{an}.ap\)
While the unary operators \(an, ap, \overline{an}, \overline{ap} \) are the ternarytobinary decoders, the output of the function is obtained by a binarytoternary encoder. (\(y_1\) and \(y_2\) are the binary inputs of this encoder.)
Synthesis of a ternary full adder
The truth table of a ternary full adder is presented in Table 4. A, B and S are the ternary inputs and output, while \(C_{\rm in}\) and \(C_{\rm out}\) are the binary carries. It should be mentioned that ternary adders have binary carries and not ternary ones. While ternarytobinary decoding and binarytoternary encoding are mandatory, there are two opposite techniques to implement a ternary adder.
Direct implementation
The direct implementation corresponds to the general scheme of mvalued circuits presented in Fig. 3. The following notations are used: Ai/Bi/Si corresponds to A/B/S=i (i=0,1,2). According to Table 4, when \(C_{\rm in}\)=0, then

\(S0_{C0} = A0B0+A1B2+A2B1 \)

\(S1_{C0} = A0B1+A1B0+A2B2\)

\(S2_{C0} = A0B2+A1B1+A2B0\)

\(C_{outC0} = A2B1 + A1B2+A2B2\)
When \(C_{\rm in}\)=1, then

\(S0_{C1}\) = S2\(_{C0}\)

\(S1_{C1}\) = S0\(_{C0}\)

\(S2_{C1}\) = S1\(_{C0}\)

\(C_{outC1}\) = A2+B2+A1B1
In any case,

\(A0=An, A1=\overline{An}.Ap, A2=\overline{Ap}\)

\(B0=Bn, B1=\overline{Bn}.Bp, B2=\overline{Bp}\)
The methodology used to implement and simulate the ternary circuits will be detailed in the section Methodology. For the moment, we just mention

CNTFET technology is used. It has the same circuit styles than CMOS technology.

Ternary circuits are implemented with two power supplies V\(_{dd}\) and V\(_{dd}\)/2 as ternary circuits with only one power supply exhibit static power dissipation for level 1.
Two possible implementations can be considered for the direct approach:
Implementation with A0, A1, A2, B0, B1, B2
The corresponding sum circuit is shown in Fig. 4. It directly corresponds the previously written equations. The circuit is divided in three parts.

A and B ternary inputs are decomposed into A0, A1, A2, B0, B1 and B2 binary outputs. \(A_n\), \(A_p\), \(B_n\) and \(B_p\) are the outputs of the circuits shown in Fig. 1 that implement the unary functions of Table 1. The inverters and NOR gates use the typical CMOS circuit style.

The second binary part first computes \(\overline{S0_{C0}}\), \(\overline{S1_{C0}}\), \(\overline{S2_{C0}}\) using complex gates (combination of series/parallel patterns of transistors). Two multiplexers are controlled by \(C_{\rm in}\) switches \(\overline{S0_{C0}}\), \(\overline{S1_{C0}}\), \(\overline{S2_{C0}}\) outputs to a and b inputs of the final encoder.

The final encoder is presented in Fig. 2.
With the same approach, the corresponding \(C_{\rm out}\) circuit is shown in Fig. 5.
The overall transistor count is 74 T + 44 T = 118 T.
Implementation using An, Ap, Bn, Bp
It could be observed that

\(A0=An, A1=\overline{An}.Ap, A2=\overline{Ap}\)

\(B0=Bn, B1=\overline{Bn}.Bp, B2=\overline{Bp}\)
The sum circuit can be implemented from \(A_n\), \(A_p\), \(B_n\) and \(B_p\) and the corresponding complemented values (Fig. 6). The binary part is similar to the corresponding part in Fig. 4 except that some AND gates have 3 inputs instead of 2 (\(A1=\overline{An}.Ap\) and \(B1=\overline{Bn}.Bp\)). The corresponding carry circuit is shown in Fig. 7.
The overall transistor count is 82 T + 46 T = 128 T.
Comments on the direct approach
Both implementations have a huge number of transistors. It means that this approach is the worst one. There is no need to simulate these circuits. It is quite obvious that they would have large propagation delays and large chip area.
MUXbased implementation
The MUX approach is based on a different way to consider Table 4:
When \(C_{\rm in}\)=0

When B=0, then Sum=A

When B=1, then Sum = (A+1) mod(3) quoted as \(A^{1}\)

When B=2, then Sum = (A+2) mod(3) quoted as \(A^{2}\)

When B=0, then \(C_{\rm out}\)=0

When B=1, then \(C_{\rm out}\)=1 when \(A=2\) else 0

When B=2, then \(C_{\rm out}\)=1 when \(A>0\) else 0
When \(C_{\rm in}\)=1

When B=0, then Sum=\(A^{1}\)

When B=1, then Sum=\(A^{2}\)

When B=2, then Sum= A

When B=0, then \(C_{\rm out}\)=1 when \(A=2\) else 0

When B=1, then \(C_{\rm out}\)=1 when \(A>0\) else 0

When B=2, then \(C_{\rm out}\)=1
Postunary functions (Table 1) are implemented by the threshold detectors shown in Fig. 1. The \(A^{1}\) and \(A^{2}\) operators (Fig. 8) are derived from \(A_n\) and \(A_p\) outputs of the threshold detectors. So the ternarytobinary decoding (threshold detectors) and binarytoternary encoding (\(A^{1}\) and \(A^{2}\)) process is limited to the generation of \(A^{1}\) and \(A^{2}\) outputs. Then, two 3input MUXes are controlled by B switch A, \(A^{1}\), \(A^{2}\) to \(Sum_0\) and \(Sum_1\). Two other 3input MUXes are controlled by B switch different binary carry values to \(\overline{C_{out0}}\) and \(\overline{C_{out1}}\). It should be noticed that these binary values are 0/2. One final MUX controlled by \(C_{\rm in}\) switches either \(Sum_0\) or \(Sum_1\) to Sum, while another one switches either \(\overline{C_{out0}}\) or \(\overline{C_{out1}}\) to \(\overline{C_{\rm out}}\). The final 1/0 \(C_{\rm out}\) is obtained using an inverter with V\(_{dd}\)/2 power supply.
The 3input MUX circuit is shown in Fig. 9. The 2input final MUXes are controlled by a binary value (\(C_{\rm in}\)). They use the typical 2input MUXes with binary control.
In Table 4, the binary input and output carry values are 0/1, while A and B inputs have 0/1/2 values. However, when implementing ternary adders, the carry levels can be 0 and V\(_{dd}\)/2 (corresponding to 0/1 values) or 0 and V\(_{dd}\) (corresponding to 0/2 values). V\(_{dd}\) carry swing can be used as \(C_{\rm in}\) only controls the final MUXes and \(C_{\rm out}\) can also have a V\(_{dd}\) swing. There are few differences between V\(_{dd}\)/2 and V\(_{dd}\) carry versions that are outlined in Fig. 10. The V\(_{dd}\)/2 version uses a NI inverter to get \(C_{n},\) and the final carry inverter has a 0.45V power supply. For the V\(_{dd}\) version, \(C_{\rm in}\) and \(C_{\rm out}\) use inverters with V\(_{dd}\) power supply.
Some details should be mentioned:

In Figs. 9 and 10, some inverters look redundant. The point is that NI and PI inverters (Fig. 1) have poor driving capabilities. The added inverters are used as buffers.

The simplest circuit to get Sum and \(C_{\rm out}\) with final MUXes is shown in Fig. 11. However, in carry propagate adders (CPAs) shown in Fig. 12, there could be a direct propagation of carry values through a series of transmission gates with the RC effect shown in Fig. 13 that degrade the switching and propagation delays. This is the reason why an inverter is used to improve the propagation delays (Fig. 14).
The transistor counts are, respectively, 50 T (V\(_{dd}\)/2 carry values) and 48 T (V\(_{dd}\) carry values).
Related works
A lot of ternary full adders have been published in the last decade [3,4,5,6,7,8,9,10,11]. They use different techniques quoted in Table 5 that range from direct implementation to MUXbased implementation. Transistor count is not a sufficient criterion to determine the best technique. However, considering Table 5 and a similar table comparing ternary half adders in [12], the technique using A¹ and A² operators and MUXes may be considered as the most efficient one.
Methodology to compare MUXbased ternary adders and binary ones
The significant figures to compare circuit designs include switching times, power dissipation, chip area, etc. The comparison is realized by using HSpice simulations and evaluating the chip area according to transistor sizes.
CNTFET technology
All simulations are done with the 32nm CNTFET parameters of Stanford library [13] as most papers presenting designs of ternary circuits in the last period use simulations with this 32 nm CNTFET technology. This allows us to compare our results with all published results on ternary circuits. One advantage of CNTFET technology is that the threshold levels of gates only depend on the diameter of individual transistors, which facilitates the design of mvalued circuits.
Propagation delays
In full adders, the important information is the propagation delay corresponding to the critical paths, i.e., from \(C_{\rm in}\) or Inputs to \(C_{\rm out}\) or Sum. For CPAs, the critical path is \(C_{\rm in}\) to \(C_{\rm out}\), except for the first and last full adders. We will only present the propagation delays corresponding to the critical paths.
Power dissipation and powerdelay product (PDP)
Both power dissipation and PDP directly depends on the duration of the input signals. It is important to use the same input signal for all designs. For all simulations, the input waveforms shown in Figs. 15, 16 and 17 are used. It has been verified that the delays for 0–2 or 2–0 ternary transitions are always less than for ternary transitions 0–1, 1–2, 2–1 or 1–0. These waveforms are used to compute the worstcase delays from Input (A or B) to Sum/\(C_{\rm out}\) and from \(C_{\rm in}\) to Sum/\(C_{\rm out}\).
Chip area
We use a rough evaluation of the chip area by summing the diameters of all the used transistors by each circuit. This rough evaluation is a little bit better than the transistor count. In this paper, the diameter values presented in Table 6 are used.
Circuit styles
Many techniques have been proposed to design full adders. Only techniques with the following properties are considered:

No static power dissipation

The circuit outputs have full swing. Reduced swings degrade noise margins and can degrade the operation of cascaded circuits, such as CPAs

The circuits should have a sufficient driving capability.
Performance of the ternary full adder
We now present the simulation results for the two versions of the ternary full adder presented in Fig. 10: One version has V\(_{dd}\)/2 carry levels (quoted as 0.45), and the second one has V\(_{dd}\) carry levels (quoted as 0.9) as V\(_{dd}\)=0.9V.
Performance with a 2 fF capacitive load
Figure 18 presents the Input to \(C_{\rm out}\)/Sum performance with a \(C_{L}\) = 2 fF capacitive load. Figure 19 presents the \(C_{\rm in}\) to \(C_{\rm out}\)/Sum performance with the same load.
The following remarks can be made when comparing \(V_{dd}/2\) and \(V_{dd}\) carry swings

Chip areas are equivalent

For Input to \(C_{\rm out}\)/Sum performance, the 0.45V version is slightly better than the 0.9V one.

However, the 0.9V version is better for Cin to Cout/Sum performance. For \(C_{\rm in}\) to \(C_{\rm out}\) delay, which is the critical one in CPAs, the 0.9V delay is more than x2 reduced compared to the 0.45V version. The reason is that the final inverter with 0.9V power supply has more driving capability as the inverter with 0.45V power supply.
Delays and power according to capacitive load
With a log–log scale (except for \(C_{L}\) = 0 fF), Fig. 20 presents the input to outputs delays according to \(C_{L}\). Figure 21 presents the same information for \(C_{\rm in}\) to outputs delay, while Fig. 22 presents the evolution of power according to \(C_{L}\). Considering the different curves between \(C_{L}\) = 0.25fF and \(C_{L}\) = 4fF, it may be observed that the delay evolution is close to a linear one, with different slopes. Power increases more than linearly according to \(C_{L}\).
\(C_{\rm in}\) to \(C_{\rm out}\) path is through a multiplexer and an inverter, while \(C_{\rm in}\) to Sum is just through a multiplexer. The inverter restores the signal and has more driving capability than the multiplexer. It explains why the sum delay is more sensitive to capacitive load. Input to \(C_{\rm out}\) and Sum paths include the whole circuit. The final inverter delay for \(C_{\rm out}\) has a limited impact on the overall delay compared to Sum delay, which explain why these large delays do not increase much when \(C_{L}\) is multiplied by 16. Power increases from x2 to x3.
The Binary Full Adders
The considered ternary adders have 2 power supplies: V\(_{dd}\) and V\(_{dd}\)/2. It means that some transistors operate with a V\(_{dd}\)/2 voltage swing. To compare the ternary adders with binary adders, it makes sense to use two different power supplies for the binary adders: either V\(_{dd}\) or V\(_{dd}\)/2. Using V\(_{dd}\)/2 instead of V\(_{dd}\) roughly divides by four the dynamic power dissipation.
The 14T binary full adder (BFA) presented in Fig. 23 is used. It corresponds to the following equations:

Sum = a \(\oplus \) b \(\oplus \) c

If a \(\oplus \) b = 1, then \(C_{\rm out}\) = \(C_{\rm in}\) else \(C_{\rm out}\) = a
Performance with a 2 fF capacitive load
Figure 24 presents the Input to \(C_{\rm out}\)/Sum performance with \(C_{L}\) = 2 fF. Figure 25 presents the \(C_{\rm in}\) to \(C_{\rm out}\)/Sum performance with the same capacitive load. All powers for 0.45 V\(_{dd}\) are roughly 1/4 of the powers of 0.9 V\(_{dd}\) versions, leading to PDP slightly smaller or equivalent for both V\(_{dd}\). In [17], this binary adder has been compared with two other ones: the 28T typical CMOS implementation and a 34T MUXbased implementation. The simulated BFA (Fig. 23) is globally the most efficient one in terms of delays, PDP and \(\Sigma {Di}\) for the two different power supplies.
Delays and power according to capacitive load
The performance of the BFA according to capacitive loads are now presented. With a log–log scale, Fig. 26 presents the input to outputs delays according to \(C_{L}\). Figure 27 presents the same information for \(C_{\rm in}\) to outputs delays, while Fig. 28 presents the evolution of power according to \(C_{L}\). There is a quasilinear evolution of delay and power according to \(C_{L}\). However, the binary adder structure is different of the MUXbased ternary adder structure: There is one MUX for \(C_{\rm out}\), but not a series of MUXes as in the Sum output of ternary adders. Globally, the binary adder is more sensitive to capacitive loads than the ternary ones.
Comparing 6bit and 4trit Carry Propagate Adders (CPAs)
The considered MUXbased ternary and binary adders can be used to build CPAs. The most significant information is to compare CPAs computing the same amount of information. 6bit CPAs compute 6 bits of information, while 4trit CPAs computes 6.34 bits of information, i.e., 6% more information.
Several 4trit CPAs have been presented in the literature [5, 14, 15 and 16].
Both for binary and ternary adders, Input to \(C_{\rm out}\) delay is greater than \(C_{\rm in}\) to \(C_{\rm out}\) delay. In CPAs, the critical path is thus from Input to \(C_{\rm out}\) for the first adder, then \(C_{\rm in}\) to \(C_{\rm out}\) for the next ones and finally \(C_{\rm in}\) to Sum for the last one. It means that Input to \(C_{\rm out}\)/Sum provides the worstcase delays.
Figure 29 compares the performance of these two CPAs with the following variants: The ternary one uses 0–V\(_{dd}\)/2 or 0–V\(_{dd}\) carry swing, and the binary one uses V\(_{dd}\) or V\(_{dd}\)/2 power supplies. The simulation has been done with a \(C_{L}\) = 2 fF capacitive load and T = \(25^{\circ }\)C temperature. Other loads or temperatures would not change the results of the comparisons. From Fig. 29, the following conclusions can be deduced:

While the binary CPA uses more full adders, its estimated chip area is x0.45 the chip area of the ternary CPAs.

The ternary CPAs have less propagation delays when using full carry swing than when using V\(_{dd}\)/2 carry swing

The 0.45 V\(_{dd}\) binary CPAs have the smallest power dissipation, from 1/2 to 1/4 power dissipation of the other CPAs. While its input to sum delay is the worst one, this CPA has the lowest PDP both for sum and carry outputs.
While ternary CPAs have less full adders, they suffer from larger chip areas and do not provide significant advantages in terms of delays. The best CPA is the binary one with V\(_{dd}\) = 0.45V supply. Reducing power supply is possible with binary circuits, but is not possible with ternary circuits, as they would need a larger V\(_{dd}\) to handle the different voltage levels.
In this paper, binary and ternary CPAs have been compared. The overall results are similar for quaternary CPAs [17]. Paper [18] also shows that binary multipliers are more efficient than quaternary ones. It means that binary circuits are more efficient than ternary or quaternary ones to implement combinational circuits.
Concluding remarks
The ordered set of ternary values (\(0<1<2\)) implies using some flavor of Post algebras. The monotonic Post algebra is the best form to implement ternary circuits. With totally ordered set of values, ternary values should be decomposed into binary values (threshold decoders) and the binary values should be encoded as ternary values. Using binary computation within ternary circuits cannot be avoided. Two opposite approaches to implement ternary adders have been detailed:

The naive approach decomposes A and B ternary inputs into binary Ai and Bi for which Ai/Bi=2 when A/B=i (else Ai/Bi=0). Then, S0, S1 and S2 binary outputs are computed as functions of A0, A1, A2, B0, B1, B2. Finally, The ternary sum is computed by the final encoder as a function of S0, S1, S2 and \(C_{\rm in}\). The output carry is computed using the same approach.

The MUXbased approach limits the ternarytobinary decoding and binarytoternary encoding to the implementation of A¹ and A² functions for which A¹=(A+1)mod 3 and A²=(A+2)mod 3. Then, the ternary values A, A¹ and A² are switched to the output sum according to B and Ci values using multiplexers. The carry output is computed using the threshold decoder outputs and multiplexers.
It turns out that the MUXbased approach outperforms the naive one. All the proposed ternary adders in the last decade fits within these two opposite approaches. The proposed and simulated MUXbased ternary adder is probably close to the best possible one. Two possible implementations differ with the carry values: either V\(_{dd}\)/2 or V\(_{dd}\). It should be mentioned that too long series of MUXes should be avoided as they degraded the switching times and propagation delays. For CPAs that propagate carries through the successive full adders, the adder carry output should be restored by an inverter.
We have evaluated the performance of this ternary adder and a 14T binary one in terms of worstcase propagation delays, power and PDP for Input to \(C_{\rm out}\)/Sum and \(C_{\rm in}\) to \(C_{\rm out}\)/Sum. The ternary and binary adders are compared with the implementation of a 6bit CPA and a 4trit CPA. These two CPAs compute approximately the same amount of information. Globally, the 4trit CPAs are less efficient than the 6bit CPAs:

The ternary CPAs use more than 2x the binary chip areas

When the ternary CPAs use a V\(_{dd}\) power supply, the binary ones can use either a V\(_{dd}\) or a V\(_{dd}\)/2 power supply. Using V\(_{dd}\)/2 power supply, the binary CPAs outperform the ternary ones in terms of power dissipation and PDP.
The fundamental weakness of ternary (and quaternary) combinational circuits comes from the mandatory ternarytobinary decoding and binarytoternary encoding that exist both at the math (Post algebra) and the circuit levels. This allows to understand why ternary combinational circuits have been unsuccessful in the last 50 years.
Circuits using an ordered set of values can be successful in small niches. It is the case of mvalued flash memories that use different levels of electrical charges. 4valued (MLC) flash memories store two bits per cell. 8valued (TLC) memories store 3 bits per cell. In 2018, ADATA, Intel, Micron and Samsung have launched some SSD products using QLD NANDmemory with 4 bits per cell. They can be used as flash memory access times are not critical. While binary flash memories have the advantage of faster write speeds, lower power consumption and higher cell endurance, Mvalued flash memories provide higher data density and lower costs
References
Post EL (1921) Introduction to a general theory of elementary propositions. Am J Math 43:163–185
Nutter RS, Swartwout RE, Rine DC (1974) Equivalence and transformation for post multivalued algebras. IEEE Trans Comput C23:294–300
Lin S, Kim YB, Lombardi F (2011) CNTFETbased design of ternary logic gates and arithmetic circuits. IEEE Trans Nanotechnol 10(2):217–225. https://doi.org/10.1109/TNANO.2009.2036845
Srinivasu B, Sridharan K (2017) A synthesis methodology for ternary logic circuits in emerging device technologies. IEEE Trans Circuits Syst I 64(8):2146–2159. https://doi.org/10.1109/TCSI.2017.2686446
Tabrizchi S, Panahi A, Sharifi F, Navi K, Bagherzadeh N (2017) Method for designing ternary adder cells based on CNFETs. IET Cir Devices Syst 11(5):465–470. https://doi.org/10.1049/ietcds.2016.0443
Shahrom E, Hosseini SA (2018) A new low power multiplexer based ternary multiplier using CNTFETs. AEUInt J Electron C 93:191–207. https://doi.org/10.1016/j.aeue.2018.06.011
Vudadha C, Surya A, Agrawal S, Srinivas MB (2018) Synthesis of ternary logic circuits using 2:1 multiplexers. IEEE Trans Circ Syst I 65(12):4313–4325. https://doi.org/10.1109/TCSI.2018.2838258
Sharma T, Kumre L (2019) CNTFETbased design of ternary arithmetic modules. Circuits Syst Signal Process 38(10):4640–4666. https://doi.org/10.1007/s00034019010709
Mahmoudi Salehabad I, Navi K, Hosseinzadeh M (2020) Two novel inverterbased ternary full adder cells using CNFETs for energyefficient applications. Int J Electron 107(1):82–98. https://doi.org/10.1080/00207217.2019.1636306
Kim S, Lee SY, Park S, Kim KR, Kang S (2020) A logic synthesis methodology for lowpower ternary logic circuits. IEEE Trans Circuits Syst I Regul Pap 67(9):3138–3151. https://doi.org/10.1109/TCSI.2020.2990748
Hosseini SA, Etezadi S (2021) A novel lowcomplexity and energyefficient ternary full adder in nanoelectronics. Circuits Syst Signal Process 40(3):1314–1332. https://doi.org/10.1007/s00034020015192
Jaber RA, Owaidat B, Kassem A, Haidar AM (2020) A novel lowenergy CNTFETbased ternary halfadder design using unary operators. In: 2020 International conference on innovation and intelligence for informatics, computing and technologies (3ICT), pp 1–6. https://doi.org/10.1109/3ICT51146.2020.9311953
Deng J, Wong HP (2007) A compact SPICE model for carbonnanotube fieldeffect transistors including nonidealities and its applicationpart II: full device model and circuit performance benchmarking. IEEE Trans Electron Devices 54(12):3195–3205. https://doi.org/10.1109/TED.2007.909043
Mahboob Sardroudi F, Habibi M, Moaiyeri MH (2021) A lowpower dynamic ternary full adder using carbon nanotube fieldeffect transistors. AEUInt J Electron C 131:153600. https://doi.org/10.1016/j.aeue.2020.153600
Hosseini SA, Etezadi S (2021) A novel lowcomplexity and energyefficient ternary full adder in nanoelectronics. Circuits Syst Signal Process 40(3):1314–1332. https://doi.org/10.1007/s00034020015192
Jaber RA Two improved designs for ternary full adders using unary operators and ternary multiplexers. Personal communication
Etiemble D Ternary and Quaternary CNTFET Full Adders are less efficient than the corresponding binary ones for the CarryPropagate Adders arxiv:2207.04839
Etiemble D CNTFET quaternary multipliers are less efficient than the corresponding binary ones arxiv:2206.03252
Author information
Authors and Affiliations
Contributions
The author read and approved the final manuscript.
Corresponding author
Ethics declarations
Competing interests
The authors declare no competing interests.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
About this article
Cite this article
Etiemble, D. Post algebras and ternary adders. Journal of Electrical Systems and Inf Technol 10, 20 (2023). https://doi.org/10.1186/s4306702300088z
Received:
Accepted:
Published:
DOI: https://doi.org/10.1186/s4306702300088z