Table 2 Comparisons different multilevel inverter topologies
References | No of Switches | Techniques implemented | Symmetrical/asymmetrical/both | Merits | Demerits |
|---|---|---|---|---|---|
MLDC [6] | m + 3 | PWM switching angle | Both | Makes use of fewer semiconductor switches Optimum circuit design There is no need for additional clamping diodes or capacitors | Expenses are high since storage capacitors are used Reduced device count causes a rise in power rating, which damages the device |
SSPS [8] | 2n + 4(U) | PD-SPWM | Both | Uncomplicated design It is feasible to distribute loads uniformly Able to run as a single DC source configuration Requires fewer gate driver circuits | Inapplicable to fault-tolerant operations and unable to function as an asymmetric configuration |
T-type [11] | 4(U), n − 1(B) | FPGA | Symmetrical | The supervised structure is straightforward Diodes and capacitors are not necessary | Switching losses are substantial Low efficiency is the outcome of a high-frequency operation Cannot be used for applications requiring high voltage and/or power |
Crisscross [13] | 3n + 4 | Vertical-phase-shifted SPWM strategy | Both | The system has low PIV The capacity to function with both negative and positive voltage | Switches that can operate in both directions are necessary Operation requires an isolated input DC-link |
RV [15] | 2n + 4(U) | PD-SPWM | Both | DC-links that are not isolated are used Peak voltage and switching frequency are used to operate rated switches | Non-uniform load sharing Low levels of redundancy |
SCSS [17] | 2n + 4(U) | PWM switching angle | Symmetrical | A flexible framework Maximum voltage and switching frequency are supported by rated switches | Each switch has a different rating of voltage, which results in uneven load sharing |
MLM [18] | 4(U), n + 1(B) | Fundamental frequency switching technique | Symmetrical | Can function with fewer DC source voltages Needs smaller amount of power diodes, transistors, and semiconductor switches | Flops when used in an asymmetrical arrangement Separate DC sources are necessary |
2SELG [20] | 2n + 4 | Staircase control method | Symmetrical | Only a few switches are required Uncomplicated structure | Does not work at the basic switching frequency Intricate control Needs separate DC sources |
Cross-connected [22] | 2n + 2(U) | Multicarrier PWM scheme | Both | Need fewer switching devices and fundamental sub-inverter cells For a specific level, it requires the least blocking voltage | Only works with solitary DC sources A need for on-state switches Not very economical |
PUC [23] | 2n + 2(U) | Sinusoidal PWM modulator | Both | The architecture is straightforward The potential for further crossover switches | Various switches have varying voltage ratings Applications that can tolerate errors cannot exist Implementation expenses are higher |
CBSC [24] | 2n + 2(B) | Fundamental frequency switching technique | Both | Decreased operating costs Basic circuit | Not possible to use asymmetric topology |
E-type [25] | 6n(U), 2n(B) | Selective harmonics pulse width modulation | Asymmetrical | Absolute asymmetry Switching redundancies are produced through cascading | Significant device decrease Voltage balancing with DC-link is challenging |
ST-type [26] | 6n(U), 3n(B) | Nearest level control | Asymmetrical | Switch count is lower than for the E-type | Notable device reduction |